Devin K. Brown

Senior Research Engineer

Microelectronics Research Center

EDUCATION:

6/95 Master of Science in Electrical Engineering, Georgia Tech

6/93 Bachelor of Electrical Engineering with High Honor, Georgia Tech

EXPERIENCE:

7/02 - present: Senior Research Engineer, Georgia Tech, Atlanta, GA

• developed 100kV e-beam lithography (EBL) processing, achieved 6.5nm resolution in hydrogen silsesquioxane negative electron beam resist
• developed EBL process for carbon nanotube growth catalyst, successfully growing vertical and horizontal single walled nanotubes
• developed EBL baseline processes and training program for over 39 internal and external research groups enabling their research goals. work consists of characterizing ebeam exposure of 3 different resists, and supporting processes such as metal evaporation, plasma etching, etc.
• support advanced nanoindentation measurements of nanometer scale film stress, hardness, and modulus characterization as well as MEMS characterization and advanced electro-optical I/O
• developed process for fabricating sub-micron photomasks
• main support for KLA P15 contact profilometer and Unifilm metal sputter deposition. oversee trainers and application support
• supported evaluation of advanced field emission SEM acquisition
• implemented CMOS device characterization & test automation on Alessi Cascade probe station.

9/97 – 5/02: Senior Etest Device Engineer, Intel, Hillsboro, OR

• Evaluated semiconductor fab process conditions and used device physics knowledge to optimize CMOS transistor ION/IOFF performance to maximize Pentium family microprocessor operating frequencies (> 2 GHz)
• Using Cadence Opus, coordinated layout and development of CMOS semiconductor devices for monitoring product and process design rule health (DRC, Hercules)
• Identified problems with photolithography patterning due to optical proximity correction (OPC) algorithm errors in order to improve transistor performance on small feature devices.
• Provided feedback to VLSI design engineers on semiconductor process impacts/limitations on performance of new product introductions (NPI)
• Helped qualify and analyze process window for new Cobalt salicide process for 70 nm linewidths.
• Performed front end transistor (0.13 µm, 18Å oxide) and back end 6 metal layer parametric design rule analysis in order to qualify and characterize new processes (DOE).
• Performed root cause analysis of Etest parametric failures and used multivariate analysis to identify responsible semiconductor fab process operations in order to continuously improve line yield and ensure quality and reliability.
• Used general statistic skills to monitor and control process health (SPC)
• Developed empirical model to predict microprocessor frequencies 6 weeks before product completed allowing quick response to in fab excursions.

6/97 - 4/98: Course Instructor, Portland Community College, Hillsboro, OR

• while working at Intel, taught part time college level instruction of fundamental Boolean algebra and digital electronics to 10-15 students per quarter both in a classroom and laboratory setting.

7/95 – 8/97: Ion Implant Process Engineer, Intel, Aloha, OR

• Qualified Varian E500 and 180XP Ion Implanters for bipolar & CMOS process using metrology such as SIMS, V/I, and Therma-wave
• Managed individuals and teams to meet IC manufacturing output, yield goals, while properly planning and executing area improvement projects. Met ISO 9002 certification and criteria.
• Worked with E-test and Integration engineers to solve semiconductor device performance problems by doing recipe parameter investigations and split lot analysis.
• Proactively reduced particle defect mechanisms.